1. Field of the Invention
The invention relates in general to a power management process in an advanced configuration power interface (ACPI) computer system, and more particularly, to a method of increasing system execution stability of the power management process by synchronizing the operation frequencies of system random access memory (RAM) and the central processing unit (CPU) while a executing power management process in the system management mode (SMM).
2. Description of the Related Art
Power management techniques such as the advance power management (APM) have been broadly applied to personal computers. For the current computer system, most of the system basic input/output systems (BIOS) and process systems provide functions to support power management. The power management process is performed via the BIOS program stored in the system read only memory (ROM). When a power management event or a power configuration event (such as a request to convert a “work” state into a “sleep” state) occurs to the legacy OS system, an interrupt of OS-transparent is generated to the power management event or power configuration. This is called system management interrupt (SMI). The BIOS receives the notice of interrupt event via the system management interrupt. While the event occurs, the BIOS communicates with the operating system to generate a system management interrupt to the CPU after the operating system acknowledges all the OS level device drivers, so as to transfer control to the system BIOS. The system BIOS is responsible for processing the required software state information and controlling the related hardware to complete the request. When the system wakes up by a wake-up event, the BIOS again receives notice from a system management interrupt. All the required resume operations of the hardware state information are executed before returning control to the operating system.
In the later ACPI computer system, when a power management event or a power state event occurs, an interrupt which has to be shareable and OS-visible is generally generated. This interrupt is called the system control interrupt (SCI). The operating system guides a power state change for the entire system and apparatus. Nowadays, the ACPI has become the key device for operating system directed configuration and power management (OSPM).
The ACPI comprises several listings, a BIOS and a hardware register. The ACPI listings (definition blocks) are used to describe the system state information and the control method. The ACPI BIOS is a part of the system firmware that completes the interfaces of specified listings, sleep, wake-up, and reset operations to store the permanent change of the ACPI tables. The ACPI register is to store and transmit the event information between the hardware, the firmware and the ACPI driving program. The ACPI driving program is an OS-level software program to coordinate the transaction between the working state and the sleeping state.
The ACPI specification defines a global working state G0, in which the host CPU can execute the BIOS command. Under such state, the peripheral apparatus can dynamically change the power state thereof The ACPI specification farther defines a global sleeping state G1. Under the state G1, the CPU does not execute any user mode thread. The G1 state comprises sleeping five states S1 to S5 for the computer system. In the S3 sleeping state (which is the called the STR state for the legacy AMP OS, and AMP is a short form of suspend to RAM), it defines that the power other than the one to reserve system memory is not existent. Before the system enters the sleeping state, the BIOS stores all the system hardware (including CPU, cache memory and chipset) configuration information and contexts into the system management RAM (SMRAM) of the system memory. Only the low voltage power (of about 5V) supplied to the system memory and the south bridge chipset is reserved. When a wake-up event is detected, the BIOS resumes all the hardware configuration and enables the hardware operation according to the information stored in the system management RAM.
However, while performing power management process, should inconsistency between the operation frequencies of the CPU and the system RAM occur, operations of the system RAM and the CPU cannot be synchronous. More seriously, the computer system may crash while performing power management process.